High-Speed Printed Circuit Boards (PCBs) and Manufacturing

ABSTRACT

High speed printed circuit boards (PCBs) are disclosed comprising a dielectrics systems with the back-side trenches, prepregs, signal lines and ground-plans, wherein the signal line and ground-plan are located on the dielectrics. Using of the open trenches in the substrate help to reduce the microwave loss and dielectric constant and thus increasing the signal carrying speed of the interconnects. Thus, according to the present invention, it is possible to provide a simple high speed PCB using the conventional material and conventional PCB manufacturing which facilitates the design of circuits with controlled bandwidth based on the trench opening in the dielectrics, and affords excellent reliability. According to this present invention, high speed PCB with the interconnect system contains whole portion or portion of interconnects for high speed chips interconnects and that have have the dielectric system with opened trench or slot to reduce the microwave loss.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication No. 60/522,021 filed on Aug. 3, 2004.

FIELD OF INVENTION

This invention relates to high speed electrical interconnects forchip-to-chip interconnection, more particularly on the high-speedprinted circuit board (PCB), where two or more integrated circuits (ICs)are needed to connect each other's signal lines for communicating. Thesetypes of high speed PCBs (also covering printed-wiring-board (PWB))could be used in all kinds of computers covering from personnel computerto super-computer, server, storage system, game system, imaging systemand networking systems. This invention is also related to the high-speedelectrical interconnection, optical interconnection or both electricaland optical interconnection where PCB is used for two or more high-speedelectronics and/or optical elements connection.

BACKGROUND OF INVENTION

The increasing of higher level of integration within electricalintegrated circuit (IC) leads to both higher data rates and largernumber of IC interconnections. Today, the inherent signal speed of IC isincreased to 3 GHz, and shortly it will be reached to 10 GHz and beyond.The number of pin connection is also increased, with single IC requiringclose to 2000 interconnection (i.e. single processor), and shortly itwill be increased to over 5000. Simultaneously achieving higher datarates and higher interconnects densities for off-chip, will beincreasingly difficult as the IC technologies continue to evolveincreasing signal speed of electronic devices and interconnectionnumber. In off-chip case, high density interconnects, covering fromdie-level packaging to chip-to-chip (hereafter chip indicates the diewith package) interconnection on the PCB, will also be gettingincreasingly difficult as the IC technologies continue to evolveincreasing the signal speed and interconnection number.

With increasing of the signal speed and interconnection number of theIC, low-cost high-speed interconnect technique compatible to today'smanufacturing process are highly desirable to make available in consumerlevel. Today's PCB is mainly made of uniform epoxy-glass composite(Trade name: FR4) material, and their manufacturing technology alongwith PCB manufacturing are so well matured that, for long run, allsystem vendors like to use FR4 based PCB to keep the system cost low.However, FR4 has material characteristics, which limit its usage in highspeed if conventional interconnection structure is used. The reason isthat conventional FR4 has the high dielectric loss which mainly limitthe bandwidth of the interconnects.

FIG. 1 is the schematic showing a part of conventional PCB. Forsimplicity in understanding, portion of the PCB is only shown here.Conventional PCB 10 consists of single or multilayer of uniform corelayers 12, prepreg (shorthand expression for “Pre-impregnated”, used forstacking multilayers) 14, signal lines 16, and ground 18. The core layer12 could be any uniform dielectric layer. Usually, FR4 (trade name) isused as the core layer for conventional PCB. The prepreg 14 is an epoxyresin used in between the core layers 12 to stack the multiple corelayers. The high-speed electrical signal flow through the signal lines16 laid on the core layers 12 and the ground line 18 is laid oppositeside of the core layer 12. The thickness H, core layers relativedielectric constant ε, metal thickness T; and the width W of the signallines determine the impedance of the signal line. The signal lines 16can be the microstrip line type signal line 16A or stripline type signalline 16B, as shown in FIG. 2. Noted here that signal line is alsomentioned as the interconnect line or simply mentioned as theinterconnects. In conventional PCB, the microstrip line type signal line16A in which the ground 18 is separated by the uniform/homogeneousdielectric (core) layer 12A. Stripline type signal line 16B is also usedin conventional PCB, in which the signal line 16B is embedded into thehomogeneous dielectric layer 12B, and both sides the ground 18 is used.

Conventional PCB 10 as shown in FIG. 1 is manufactured in the way, theflow chart of which is shown in FIG. 3. This is an explanatory diagramfor the prior art of PCB manufacturing. The dielectric sheet 20 is madeusing the standard PCB technology for example using the slurry castingprocess. The slurry is cast into about 200 μm to 500 μm thick ceramicsheets by slip cast process. The PCB core layer 12 is the homogeneouslayer usually used in the conventional PCB 10. After the patterning andsubsequent etching, the signal line is made on side of the core layers.Micro-via and subsequent filling process 24 is done, if necessary.Following this, the sheets 26 are laminated together by hot press toform the PCB 28. Density heterogeneities in the laminated samplesinfluence any shrinkage in the sintered substrate. Therefore, thislamination process is homogenously carried out by means of the correctdimensional die and punch with flat surfaces. Burn out and sinteringprocess for the multi-layered PCB board 10, may necessary afterlamination at the temperature suitable to ceramic material used as thesheet. The via hole opening and subsequent metal filling (not shownhere) are usually done. A ceramic sheet 20 may have more than 10,000 viaholes in a 50 to 250 μm square area.

In conventional PCB 10, as the signal line 16 is either laid on thedielectric material (core layer 12) or embedded into the dielectrics,based on the dissipation factor (tangent loss) of the dielectricmaterial used as the core layer in the PCB, the signal experiencesdissipation while propagating through the signal line 16. The reason isthat the electric field starts from signal line and ends in the ground18 (not shown) and this electric field is passed through thedielectrics. This signal dispersion is proportional to the signalfrequency, i.e., signal speed. It does mean that the higher the signalspeed, the lower the distance of transmission of signal for the fixeddielectric material. In the other words, the higher the speed, the lowerthe bandwidth of the signal line which is used for connecting the onechip to other chip on the board. If the tangent loss of the dielectricsare high, the bandwidth of the interconnects gets so limited that, highspeed signal can't be sent over longer distance as compared with thedielectrics having the lower tangent loss.

In addition to tangent loss, the dielectric constant of dielectricsmaterial is also important, as electrical field inside dielectricmaterial having higher dielectric constant experiences more signal delayas compared with that of transmission line comprising with lowerdielectric constant material. These causes signal skews for thedifferent length of signal lines. In this case also, lower dielectricconstant material is necessary in the interconnection for high-speedsignal interconnection. This is true for both on-chip and off-chipinterconnection. Lower dielectric constant material with low dielectricloss offers following functions; (1) Higher density interconnection ispossible due to reduction of the cross talk, (2) reducing thecapacitance of the interconnection, helping to transfer the signallonger distance, and (3) lower propagation delay.

Considering signal loss and signal delay for various signal line lengthit is highly desirable to design the interconnects on PCB whose theeffective dielectric constant and effective loss of the interconnectsystem are lower.

It is very straight forward that increasing the bandwidth can bepossible using of the material having the lower loss tangent (alsomentioned as dielectric loss or loss tangent). However, in this case,for off-chip interconnection new material development is necessary.Besides, manufacturing technology is needed to develop to implement inthe product level. Conventionally, to increase the interconnectsbandwidth, dielectrics having lower tangent loss is used as the PCBlayer. This dielectric material is very high cost and the manufacturingprocess for building PCB using these materials are not matured yet. Inaddition, the PCB made of such low loss material has low reliability. Itis highly desirable to have high speed PCB that can be built up with theconventional well-matured dielectric material (for example FR4) and alsoconventional well-matured fabrication process can be used. This can notonly reduce the cost, but also have high reliability.

Much work can be found in off-chip interconnection technology focusingon the material development. As for example, low loss materials likePolytetrafluoroethylene (PTEF), Duroid, and Rogers 4003 etc. are underdevelopment stage, to achieve high bandwidth. Implementing new materialin PCB fabrication process will cost tremendously high (more than tentimes over conventional solution) to make it mature. In addition, newmaterials having low tangent loss is a material incompatible withconventional dielectric material such as FR4 processing, so is not a lowcost solution. These materials will require a much higher temperatureand pressure for lamination. Today, in developing the high speed PCB,more focused are being paid on shortening the length or on theinterconnection layout. In both cases, implementing technology wouldneed to pay high cost.

As explained above, the conventional PCB technology being used foroff-chip interconnection couldn't be used as the need of the signalspeed is increasing. And also existing conventional electricalinterconnects have the limitation of achieving the bandwidth in certainlevel, beyond that complete manufacturing technology is needed to bechanged which is costly for PCB industries. It is highly desirable tohave lower dielectric constant and lower dielectric loss by adopt atechnique or method which can be easily implemented, and which can usethe standard dielectric material PCB technology.

SUMMARY OF INVENTION

Accordingly, it is an object of the invention to provide the techniqueto reduce the effective dielectric constant and effective dielectricloss of interconnection system especially dielectric material, toincrease the bandwidth of the interconnection for building high speedPCB.

Accordingly, it is an object of this invention to use the inhomogeneousdielectric system to reduce the effective dielectric loss and dielectricconstant of the dielectric material.

According to the invention it is an object to provide theinterconnection structure where large portion of the signal(electromagnetic wave) is allowed to pass through the air or dielectricmaterial having the dielectric loss less than the base dielectricmaterial itself on which the signal line is laid out.

It is an object of this invention to provide the manufacturing processof the high-speed PCB carrying the high-speed signal lines.

Another object of the present invention is to provide theinterconnection structure for chip-to-chip (off-chip) interconnection onthe board, which is compatible to available PCB technology.

According to the invention, the high speed PCB for off-chipinterconnection comprises, (i) single or multiple electrical signallines for carrying the electrical signal from one electronics elementsto another and vice-versa for electrical communication; (ii) single ormultiple dielectrics which are in stacked by prepreg (epoxy) wherein thedielectric system carrying the signal lines has structure comprisingwith back slot or open trenches with deepness and width, and locatedunder the signal line (conductor); (iii) a ground or power line locatedto opposite side of the dielectrics wherein the shape of the back-slotor trench could be rectangular or square or circular or any shapesconvenient for manufacturing, and covering the width the same, or lessor more than the metal conductor carrying the signal.

According to this invention, the signal line of microstrip line typeconfiguration has one open trenches under the signal lines, and thesignal lines of strip-line configuration has the opened trenches locatedtop and bottom of the dielectrics.

According to this invention, the interconnects can be of any or themixer of the transmission line configuration such as co-planar type,microstrip-type, or strip-line type.

According to this invention, it is our object to provide the structureof the opened-trenches under the signal lines of the high speed PCB.According to the invention it is an object to provide the via structureto connect the two or more layers of high speed PCB considering bothfrom manufacturing point of view and also from the impedance point ofview.

According to this invention, high speed PCB process comprises, (i) firstsingle or multiple core layers formation having copper layer in only oneside; (ii) making the signal lines in single or multiple core layers;(iii) opening the trenches in opposite side of the signal lines, whereinthe trench depth is decided from the bandwidth required for theinterconnects and the trench width can be selected based on theconvenience in manufacturing and the requirement in interconnectsbandwidth; (iv) second formation of the prepreg (epoxy) to make stackingof two or multiple core layers to make multi-layered PCB; (v) hot pressand lamination for stacking the sheets, and; (vi) sintering undertemperature.

According to this invention, the process for PCB having the signal lineof microstrip line configuration, comprises, (i) first core layerformation having copper layer in only one side; (ii) making the signallines in the first core layer; (iii) opening the trenches in oppositeside of the signal lines located on first core layer, wherein the trenchdepth is decided from the bandwidth required for the interconnects andthe trench width can be selected based on the convenience inmanufacturing and the requirement in interconnects bandwidth; (iv)formation of the prepreg (epoxy) layer to make stacking of two corelayers to make microstrip line type signal lines on PCB; (v) second corelayer formation having copper layer in only one side of the core layer;(vi) hot press and lamination for stacking the first core layer, prepraglayer, and second core layer with uniform copper layer, and; (vii)sintering under temperature.

According to this invention, the process for PCB having the signal lineof strip line type configuration, comprises, (i) first core layerformation having uniform copper layer in only one side; (ii) making thesignal lines in the first core layer; (iii) opening the trenches inopposite side of the signal lines located on first core layer, whereinthe trench depth is decided from the bandwidth required for theinterconnects and the trench width can be selected based on theconvenience in manufacturing and the requirement in interconnectsbandwidth; (iv) second core layer formation having uniform copper layerin only one side; (v) opening the trenches in opposite side of theuniform copper layer (of second core layer), wherein each trenchesposition is the same as that of the trenches made in the first corelayer and the trench depth is decided from the bandwidth required forthe interconnects and the trench width can be selected based on theconvenience in manufacturing and the requirement in interconnectsbandwidth; (vi) third core layer formation having uniform copper layerin only one side of the core layer; (vii) formation of two prepreg(epoxy) layers to make stacking of two core layers to make microstripline type signal lines on PCB; (viii) hot press and lamination forstacking the second core layer with trenches, prepreg, first core layer,prepreg layer, and third core layer, and; (ix) sintering undertemperature.

According to this invention, the electrical signal line could bemicrostrip type or strip line type or coplanar type waveguide.

According to the invention, the dielectric material having lowerdielectric loss than the dielectric material on which the signal line isdrawn, can fill the trench or back-slot of the dielectric system.

Alternatively, according to the invention, the trench or back-slot ofthe dielectric system can be filled with air or kept in vacuum.

According to the invention, alternatively the trench or back-slot of thedielectric system can be filled with the liquid crystal material, whichcan tune the dielectric constant and loss.

According to this invention, the opened trench can be filled with thecoolant to cool the PCB.

According to this invention, the high-speed communication can bepossible between two or among more than two electrical (or optical)elements where electrical, optical or both electrical and optical signalare used for transmission through the interconnects. According to thisinvention, the effective loss tangent and effective dielectric constantof the dielectric system is reduced, which reduce the microwave-loss andmakes to increase the interconnects bandwidth for high speed electricalsignal propagation, and also reduce the signal propagation delay. Thelower the microwave loss to zero, the closer to be the electromagneticwave to the speed of the light.

This invention offers to fabricate the high speed PCB (which can be usedto connect the signal lines of two or more chips among each other tocommunicate without sacrificing each inherent signal speed. The highspeed PCB embedding with the high speed interconnects can be easilyfabricated using conventional PCB manufacturing technology. The methodsdescribed in this disclosure enables to make the electronicsinterconnects for inter-chip connection in cost-effective manner andsuitable for practical application.

Other object of this invention is to minimize the skew in the signalinterconnection, occurred due to the signal propagation delay, byreducing the microwave loss.

Other objects, features, and advantages of the present invention will beapparent from the accompanying drawings and from the detaileddescription that follows below.

BRIEF DESCRIPTION OF DRAWINGS

The invention will be explained in more detail in conjunction with theappended drawings wherein,

FIG. 1 is the cross-sectional view showing the prior art of the PCB usedfor electrical connection of two or more chips. For simplicity, enlargedview of a multilayerd PCB is shown.

FIGS. 2A and 2B are the cross-sectional views showing prior art ofelectrical signal lines used in PCB for inter-chip (off-chip)connection.

FIG. 3 is the schematics illustrating the prior art fabrication processof the PCB.

FIG. 4 is the cross-sectional view showing the high speed PCB used foroff-chip interconnects in a first preferred embodiment according to theinventions. For simplicity, enlarged view of a multilayered PCB isshown.

FIGS. 5A and 5B are the cross-sectional views showing the electricalsignal lines embedded into the high speed PCB for off-chip connection inthe second embodiment according to this invention.

FIG. 6 is the schematic illustrating the fabrication process of thesignal line of microstrip line configuration used in the high speed PCBin the third embodiment according to this invention.

FIG. 7 is the schematic illustrating the fabrication process of thesignal line of stripline configuration used in the high speed PCB in thefourth embodiment according to this invention.

FIG. 8 is the schematic illustrating the fabrication process of the highspeed multilayered PCB with embedded high speed interconnects (signallines), in the fifth embodiment according to this invention.

FIG. 9 is the schematic illustrating the structure of the via structureused in the high speed PCB, in the sixth embodiment according to thisinvention.

FIG. 10A and 10B are the schematics illustrating the top view of thesignal lines on the high speed PCB, in the seventh embodiment accordingto this invention; The transition of signal lines layout is shown, whichis considered from manufacturing point of view and also keeping theimpedance constant along the signal line to Via.

FIG. 11 is the schematics illustrating the shape of the opened trenchesunder the signal lines used in the high speed PCB, in the eighthembodiment according to this invention.

FIGS. 12A, 12B, and 12C, are the graphs showing the variation of thedielectric constant and dielectric loss as a function of the dielectricremoval for trench opening, in the ninth embodiment according to thisinvention. This is an explanatory diagram to show the advantage of thisinvention. In this calculation, FR4 is considered as the PCB'sdielectric material.

FIGS. 13A and 13B are the graphs showing the variation of the dielectricconstant as function of the signal line width with various dielectricslayers thickness as the parameters, in the tenth embodiment according tothis invention. This is an explanatory diagram for the microstrip typesignal lines, to show the advantage of this invention. Design can beperformed in various ways to get the maximum benefits of theseinventions. In this calculation, FR4 is considered as the PCBsdielectric material.

FIGS. 14A and 14B are the graphs showing the variation of the dielectricconstant as function of the signal line width with various dielectricslayers thickness as the parameters, in the tenth embodiment according tothis invention. This is an explanatory diagram for the stripline typesignal lines, to show the advantage of this invention. Design can beperformed in various ways to get the maximum benefits of theseinventions. In this calculation, FR4 is considered as the PCBsdielectric material.

FIG. 15A is the graphs showing the bandwidth of the interconnects forvarious percentage of the dielectrics removal under the signal lines, inthe eleventh embodiment according to this invention. This is anexplanatory diagram to show the advantage of this invention. Design canbe performed in various ways to get the maximum benefits of theseinventions. In this calculation, FR4 based PCB with 30 cm in length isconsidered in the calculation.

FIGS. 16A is the top view and 16B and 16C are the side and frontcross-sectional views along AA″ and BB″ direction of FIG. 16A,illustrating the interchip (off-chip) interconnections consisting of themultilayered high speed PCB in the twelfth preferred embodimentaccording to the present invention.

FIGS. 17A is the top-view and 17B and 17C are the side and frontcross-sectional views along AA″ and BB″ directions of FIG. 17A,illustrating mountable/stackable the interchip (off-chip)interconnections consisting of the multilayered high speed PCB in thethirteenth preferred embodiment according to the present invention.

DETAILED DESCRIPTION

The best modes for carrying out the present invention will be describedin turn with reference to the accompanying drawings. In the followingdescription, the same reference numerals denote components havingsubstantially the same functions and arrangements, and duplicateexplanation will be made only where necessary.

An important point of high speed PCB having high speed electricalinterconnects according to the first embodiment is that the microwaveloss is to be reduced by reducing the effective tangent loss, resultingin increasing the bandwidth of the interconnects and keeping thesignal-speed of the interconnection system closer to the source speed.Other point is also kept in mind that the technique is to be costeffective, and compatible to standard manufacturing technology can beused.

In interconnects system for two or more electronics elements (two ormore chips etc.) Connections, the signal can be conveyed electricallythrough the wire (electrical conductor) laid on the dielectric medium.For high speed signal transmission electrical conductor is to betransmission line of type microstrip or strip line. The signal speed inthe interconnects (i.e. bandwidth of the interconnects system) is mainlydominated by; (a) signal conductor parameters (i) length and (ii)thickness, and (b) dielectric material properties (i) dielectricconstant, and (ii) loss tangent. Longer interconnect length willincrease the capacitance by AεL/d, where A is the area of the signalconductor, ε the dielectric constant of the material, and d thethickness of dielectric material. With optimized design, capacitance ismostly limited by the dielectric constant. As frequency increases thesignal is started to attenuate due to the skin effect. For example Cu at100 GHz, the skin-depth (δ)=0.2 μm. For comparatively lower frequency,this skin-depth can be neglected. Therefore, bandwidth of theinterconnect system is mainly dominated by the dielectric materialproperties such as dielectric constant and loss tangent. For increasingthe bandwidth of the interconnects, their values should be low.

It is very straight forward that increasing interconnects bandwidth canbe possible by using of the low dielectric loss material in off-chipinterconnects. However, new materials are needed and manufacturingtechnologies are to be developed to implement new material into highspeed PCB fabrication.

It is highly desirable to have the high speed PCB, the interconnectembedded into it should have the low effective dielectric loss anddielectric constant and such high speed PCB can be fabricated usingconventional manufacturing technology.

In the preferred embodiments explanation, first the structure of thehigh speed PCB along with the techniques to reduce the effectivedielectric constant and dielectric loss, will be explained, and laterpart of this section covers the fabrication process and some designestimations based on conventional material such as Epoxy-Glassdielectrics as the examples, related to the preferred embodiments.

(a) High-Speed PCB Structure:

FIG. 4 is the cross-sectional views of the portion of the high speedPCB, in the first preferred embodiment in accordance to the presentinvention, wherein like parts are indicated by like reference numeralsas used previously, so that repeated explanation is omitted here. Thehigh speed PCB 20 as shown in FIG. 4 consists of the four layers ofcores 12 on which two layers are for the signal lines 16A and 16B, andtwo layers for the ground (that could be used as the power or ground)18. These four core layers with signal lines and ground are stackedtogether to form the multilayered-PCB 20 by using two layers of theprepregs 14 in between of two layers of the cores. The signal lines 16Ais microstrip type and signal lines 16B are in stripline type signallines. According to this invention, in high speed PCB 20, the signallines 16A and 16B have lower dielectric loss and lower dielectricconstant as compared to those (dielectric-loss and dielectric constant)for dielectric 12, since the trenches 22 and 24 are opened under thesignal lines. The signal line 16A of microstrip type has one trench of22 under the signal and the signal line 16B of stripline type has thetwo trench openings, one 24A is in the top layer and other 24B in thebottom layer. According to this invention, the effective dielectric loss(loss tangent of dielectric system) can be reduced and the signalattenuation while propagating can be reduced. In other words, signaltransmission is less dispersive, and higher bandwidth of theinterconnects system is ascertained, as compared with the conventionalPCB where signal conductor is laid onto the uniform dielectric medium,as shown in FIG. 1 as an example of the prior art. Less cross talk isalso expected as the effective capacitance is also decreased. Based onthe design, the significant of the electromagnetic wave can be made topass through the open-trench 22 or 24. The width of the trench can beadjusted based on the signal line width. The signal line impedance canbe designed by designing the trench, dielectric layer thickness, and thesignal line width. According to this invention, the opened trenches canbe filled with the air or dielectric material (not shown) having lowerdielectric loss than the dielectric material 12.

For simplicity, in FIG. 4, trenches (22 or 24) are shown to locate closeproximity to prepregs 14 and ground 18. Alternatively, according to thisinvention, these trenches could be made at the center of dielectric 12,close proximity to signal lines (16A and/or 16B), prepregs 14, andground 18 (not shown). Alternatively, the trenches could be locatedclose proximity to the signal lines (16A and/or 16B) or close proximityto both signal lines (16A and/or 16B) and the ground 18. In FIG. 4, thetrench-widths are shown to be wider than width of the signal lines (16Aand 16B). The trench-width can be same or smaller than the signal line'swidth, and it can be selected based on the requirements of interconnectbandwidth.

FIGS. 5A and 5B are the cross-sectional views of the portion of thesignal lines of microstrip type and stripline type configurations,respectively, in the second preferred embodiment in accordance to thepresent invention, wherein like parts are indicated by like referencenumerals as used in FIG. 4, so that repeated explanation is omittedhere. In FIG. 5A, the signal lines 16A is microstrip type signal lineand it consists of two layers of the core layers 12, in which the toplayers 12 has the signal lines 16A and opened trench 22 under the signallines and the bottom dielectric layer (core) 12 has the uniform metallayer 18 which acts as the ground in the microstrip type signal line16A. In FIG. 5B, the signal lines 16B are the stripline type signal lineand it consists of three layers of the cores 12, in which the top layers12 has the ground 18 with opened trenches 24A, middle layer 12 has thesignal lines 16B with opened trench 24B aligned along with signal lines16B, and the bottom core layer 12 with the ground metal layer 18. Thesethree layers are stacked together to form the stripline type signallines. According to this invention the effective dielectric loss anddielectric constant (i.e. microwave index) are considerably decreased asmentioned in earlier. The explanation for getting the high bandwidth isalready explained in FIGS. 4, so that related explanation is omittedhere.

According to the invention, based on the interconnect structure design,the effective dielectric loss and effective dielectric constant of theinterconnect system can be controlled. This helps to add many featuresin the interconnection such as varying the phase velocity (which isfunction of the dielectric constant), varying the bandwidth of theinterconnect; help to adjust the skews of the signal etc. in the singleinterconnect system. According to the preferred embodiment, ideally, thespeed of the signal in the signal line can be made to speed of the lightin the air, if other loss due to the signal line structure such as theelectrode parameter (resistance, capacitance) are neglected. Thebandwidth of the electronic interconnect system can be possible to makethe closer or greater than optical fiber (closer to the light). In theexample, the dielectric system consisting of the opened(backside)-trench or backside slot is considered. This invention coversall high-speed PCB in which embedded signal lines as mentioned earlierare used, which is used for off-chip interconnects.

According to this invention, the high speed PCB can be designed usingsingle or plural of dielectric layer with backside opened-trench or slotunder the high-speed signal line. For simplicity, we have shown fourlayered-PCB with having two signal lines layers and two ground layers.However this present invention also includes all high speed PCB havingsingle or multiple layered PCB having the trench or slot under thesignal line to increase the bandwidth of the interconnection system.

According to the present invention, it is our object to control thepropagation of the electrical field significantly inside the trench orslot (by filling with the air or low loss (and/or dielectric constant)material which thereby increasing the bandwidth of the interconnectionsystem and reduce the signal propagation delay. In the preferredembodiments, as explained above from FIGS. 4 and FIG. 5, the strip-lineand microstrip line configuration with single or two signal lines areshown in the object of explaining the inventions. These inventions alsocover other single or multiple signal lines in other configuration suchas coplanar-line configurations. Signal lines could be single ordifferential line.

In the preferred embodiments, the dielectric layer is mentioned in anobject to cover all dielectric materials, which show the dielectricproperties. The dielectric materials include all kinds of ceramicmaterials such as Duroid, FR4, AlN, Al₂O₃, Mullite (3Al₂O₃: 2SiO₂), SiC,SiO₂, Silicon nitride, silicon carbide, Silicon-Oxy-Nitride, BeO,Cordie-rite (magnesium alumina silicate), BN, Glass (with differentcompositions), epoxy glass, CaO, MnO, ZrO2, PbO, alkali-halide (e.g.NaBr, NaCl) etc.) BN, BeO, and all kinds of low temperature cofiredceramics etc., and all kinds of the polyimides and benzocyclobutenes(BCBs) having dielectric properties. All kinds of polymer materialshaving dielectric properties falls also under this dielectric material.These dielectric materials can be made using high temperature ceramicsprocessing or using the IC fabrication process. Polymer dielectricmaterial also includes, but not limited to, Teflon, liquid crystalpolymer, epoxy, parylene, silicone-polyimide, silicone-gel, andfluorinated ethylene propylene copolymer. It also includes materials ofelastomers (e.g. silicone elastomer), monomers, and gels. Dielectricmaterials, which can be made using high temperature ceramics processingor using the IC fabrication process, also include this category. Allstandard polymers can be available from the standard manufacturer forexample, Du-pont, Hitachi-Chemical, Mitsui, and Mitsubishi-ChemicalIndustries. Gore-Tex, Japan, markets liquid crystal polymer. Polymerlike Q-PILON (Trade name) marketed by Pi R&D, Japan, also coverspolymer.

In the preferred embodiments as explained FIGS. 4 and 5, dielectricsystems having backside-opened-trench into the dielectric layer areconsidered. The opened trench could be filled up with any dielectricmaterial having lower dielectric loss and/or lower dielectric constantthan the dielectric core layer. Alternatively, the lower dielectricconstant material can be air or vacuum. Alternatively, in the preferredembodiment, trench or slot can be filled up fully by the liquid crystalmaterial or coated by liquid crystal. The electrical field can changethe orientation of the liquid crystal and can have the control of theeffective dielectric constant and dielectric loss of the dielectricsystem. This could also provide the tunability of the effectivedielectric constant and the loss of the dielectric system.

According to the present invention, the high speed PCB is made using thedielectric system, which has lower effective dielectric loss anddielectric constant. The preferred embodiments can be applied in manyapplications in different ways and forms. For examples, preferredembodiments mainly can be used for high speed PCB where interconnectsfor connecting high-speed multiple (two or more) ICs. The applicationincludes, but not limited to, (a) off-chip interconnects for example,connecting two or more electronics chips on the board, (b) high speedchip (die) packaging, and (c) high speed electrical multi-channel ribbontype flex printed circuit for connecting multiple electrical modules forexample board-to-board interconnection, rack-to-rack interconnection,etc.

In the preferred embodiments as explained below, high speed PCB processis explained in an object of showing its manufacturability using theconventional manufacturing process. (of the techniques to reduce themicrowave loss and dielectric constant to increase the bandwidth and toreduce the signal propagation delay), but not limited to, the specificdescription provided. The design estimation is also included in anobject to show the reduction of the effective dielectric constant andeffective dielectric loss factor, and the significant improvement ofinterconnects bandwidth. It is also noted here that based on thedielectrics removal, the bandwidth of the interconnects embedded intothe high speed PCB can also be adjusted.

(b) High-Speed PCB Process and Design:

Before going to explain the fabrication process of the multilayered highspeed PCB with embedding the high-speed signal lines mentioned above, wewould explain the process for the two main signal lines, which aremicrostrip type signal lines and strip line type signal lines. Themultilayered high speed PCB may have single or multiple layers of suchsignal lines embedded into the PCB.

(i) Fabrication Process for Microstrip Line Type Signal Lines

FIGS. 6A, 6B, 6C, and 6D are process steps for building the high speedPCB with microstrip type signal lines in the third preferred embodimentin accordance to the present invention, wherein like parts are indicatedby like reference numerals, so that repeated explanation is omittedhere. Enlarged cross-sectional views of a portion of high speed PCB areonly shown for explanation. In the preferred embodiment, the process forthe high speed PCB having only microstrip lines type signal linesconsists of signal lines 16A formation from uniform metal layer 25 ofthe sheet material 26, opening the trenches 22 under the signal lines16A, stacking with other sheet material 28 having one side uniform metallayer which acts as the ground 18. The stacking can be performed usingthe resin (called as the prepreg) 30 to form the multilayered high speedPCB 32 having microstrip line type signal lines. The trench 22 can beopened inside the sheet material 26 by using the laser drilling ormechanical drilling. In the case of the laser-drilling, commercialavailable the Carbon-di-Oxide (CO₂) laser or Nd: YAG laser or Excimerlaser or ultra-violet (UV) laser with variable optics arrangements canbe used. The trench deepness (Hm/n in FIG. 5, where m and n are theinteger and vary as 1, 2, 3, 4, . . . ) can be controlled by adjustinglaser intensity and pulse width of the laser illumination. Adjusting theoptics of the system can control the width. The laser technology hasbeen matured so much that today making via or microvia takes minimaltime. Several companies such as Siemens Micro Systems GmbH & Co. KG,Germany, Electro Scientific Industries, Portland Oreg., USA etc. marketthe UV, CO₂ lasers based instruments, which can do fast microvia. Forexample, CO₂ Laser, marketed by Siemens Microsystem, Germany, canmake >30,000 number of vias per min having 75 to 200 μm diameter inconventional FR4 (epoxy resin-glass) board. In the process, most time isthe off time (shifting time) from one via to other. According to thisinvention, similar laser drilling technology can be used to open thebackside trench, which is the additional process necessary in the highspeed PCB buildup process. The time will be shorter for continuousdrilling according to this invention.

According to this invention, as conventional dielectrics, FR4 (tradename of epoxy-glass) frequently used as the PCB materials can be used.In this case, CO₂ laser or YAG laser can be used for drilling to openthe trench under the trench. According to this invention, it isestimated that 160 inch of length of line having 8 mil (˜200 μm) sizecan be made by one minute, which turns to 9600 inches/hr. It estimatedthat for 4 layers of 12 inch×12 inch (30 cm×30 cm) PCB having eight 12inches MSL and eight 12 inches long strip lines. The approximated timeto make the trenches using the laser drilling is only 1.2 minutes.Electro Scientific Industries (ESI) markets the UV via machine that canetch vias at 30,000 vias per minute. This could make faster trench openwhat was estimated previously. Aligning can be done using infraredimaging analysis, which showed the metal pattern (signal lines) in theopposite side of the dielectrics.

Another method of laminate removal is using a milling machine. MITSElectronics, in Tokyo, Japan markets the milling machine, which can makethe drill in dielectrics materials, manufactured for PCB. This machinehas control in the X,Y, and Z direction. The z direction accuracy ofthis system is 0.1 mils. The instrument available in the market can makethe drilling automatically based on the trace designed. Using theavailable drilling technology, the high speed PCB can be fabricated asnoted in this invention.

According to this invention, fabrication process for the microstrip linetype signal lines are described. The similar fabrication process can beused for the high speed PCB that has only single layer of the signallines, which are the microstrip type configuration. Others layered canexist which may carry low speed signal lines. In that case, other layerscould be fabricated using the uniform dielectrics as conventional PCBfabricates. The high speed PCB could be hybridly stacked, in whichsingle or multiple layers could be dedicated using the non-uniformdielectrics (dielectrics with air trenches).

(ii) Process for Stripline Type Signal Lines

FIGS. 7A, 7B, 7C, 7D, 7E, and 7F are process steps for building the highspeed PCB with stripline type signal lines in the fourth preferredembodiment in accordance to the present invention, wherein like partsare indicated by like reference numerals, so that repeated explanationis omitted here. Enlarged cross-sectional views of a portion of highspeed PCB are only shown for explanation.

In the preferred embodiment, the process for the high-speed PCB havingstriplines type signal lines consists of signal lines 16B formation insheet material 34, opening the trenches 24B under the signal lines 16B,formation of the trenches 24A (aligned with signal lines 16B whilestacked) in the sheet material 36 having uniform metal layer which actsas the ground 18, and stacking of the sheet material 36 with trenches24A and uniform metal layer 18, sheet material 34 with trenches 24B andsignal lines 16A, and third sheet material 38 with uniform metal layer18 and uniform core layer, with the help of the two prepreg layers 40,to form the multilayered high speed PCB 42. The stacking can beperformed using the resin (called as the prepreg) 40 to form themultilayered high speed PCB 42 having stripline type signal lines. Therelated process techniques for example the patterning, trenches openingtechnique etc. are already explained in FIGS. 6, so that repeatedexplanation is omitted here.

According to this invention, fabrication process for the PCB with onlystripline type signal lines are described. The similar fabricationprocess can be used for the high speed PCB that has single or multiplelayers of signal lines, which are the stripline type configuration.Others layers may carry low speed signal lines, which may consists ofuniform dielectrics as described in the Prior Art (FIG. 1 and FIG. 2).The high speed PCB could be hybridly stacked, in which single ormultiple layers could be dedicated using the non-uniform dielectrics(dielectrics with air trenches).

(iii) Process for Multi-Layered High-Speed PCB

In the preferred embodiment as explained below, it is an object to usethe techniques as explained in FIGS. 6 to 7, in the off-chipinterconnects for multiple chip interconnection on the PCB (board). Theboard here considered is the board made from FR4 material or any otherkind of dielectric material as mentioned previously. Similar techniquecan be applicable for other dielectric material board as explainedearlier.

FIG. 8 shows the flow-chart of the high speed mulitlayered PCBfabrication process for the off-chip interconnects in the fifthembodiment in accordance to the invention, where in the like parts areindicated by the like numerals, so that repeated explanation is omittedhere. The dielectric sheet (not shown) is made using the standard PCBtechnology for example using the slurry casting process. The slurry iscast into about 200 μm to 500 μm thick ceramic sheets by slip castprocess. Each dielectrics sheet material 44 is the conventional PCB corelayer 44. Metallization sheet 46 is made using the conventional PCBtechnology. After the metallization, the trench or slot is opened insheet 48 by using the processes such as laser drilling, or dry-etchingor wet-etching (following patterning for etching) or mechanicaldrilling. Via holes are formed through the dielectric sheet 44 by apunching machine with punches and dies. A ceramic sheet 44 may have morethan 10,000 via holes in a 50 to 300 μm square area. Low resistivityconductor paste onto the punch sheet. In this process, via holes arefilled with the paste to form the contacts between the signal lines. Lowelectrical resistivity material such as silver-palladium, and goldinstead of molybdenum or tungsten refractory material can be used. Thesheets are sintered at high temperature, which makes lower electricalresistivity. The trenched sheets 48 are precisely stacked in a pressingdie in sequence by the stacking machine. These sheets 50 are laminatedtogether by hot press. Density heterogeneities in the laminated samplesinfluence any shrinkage in the sintered substrate. Therefore, thislamination process is homogenously carried out by means of the correctdimensional die and punch with flat surfaces. Burn out and sinteringprocess for the multi-layered PCB board 52, may necessary afterlamination at the temperature suitable to ceramic material used as thesheet. Additional via holes process (not shown) are necessary to connectthe signal lines located in different layers.

(iv) Via or Micro-Via Structure in High Speed PCB

In the preferred embodiment as explained below, it is an object toprovide the technique to design the via or micro-via in the high speedPCB, explained in FIGS. 6 to 8. This is one of the techniques, can beused for the case of the high speed PCB with high-speed signal lineswhere opened trenches are used to reduce the effective dielectricconstant and also to reduce effective tangent loss of the interconnectssystem. Any kinds of the board materials such as FR4 and other kind ofthe dielectric material as mentioned previously can be used as the PCBmaterial.

FIG. 9 shows the schematic showing the enlarged cross-sectional view ofa multilayerd high speed PCB with the high speed signal lines andmicro-via embedded into the PCB, in the sixth embodiment in accordanceto the invention, where in the like parts are indicated by the likenumerals, so that repeated explanation is omitted here. According tothis invention, via or micro-via 54 can be formed without damaging aboard 56 and to have sidewalls to deposit copper. To form the via ormicro-via 54, the air-cavities (opened trenches) 24A and 24B are neededto stop at some reasonable distance of (shown in FIG. 9) which isdependent on the design rule tolerant. The signal line connecting to thevia or micro-via 54 consists of two sections, (i) signal line 58 withopened trenches and (ii) signal line 60 without opened trenches prior tothe via or microvia 54. The impedance of the signal lines 58 and 60 aremaintained at the desired impedance by modifying the strip line width(not shown in FIG. 9). In this case, as the signal line 60 having thedistance of has the continuous dielectrics, for the fixed characteristicimpedance (for example 50 ohm) the metal (signal line) width is adjustedto be narrower than the metal (signal line) width of signal lines 58with opened trenches. The signal lines 58 and 60 located on core layer12D are connected to core layer 12B through the ground layer 18C whichis etched back before being stacked. According to this invention, thevia 54 is drilled or laser out or etched after core 12A, core 12B, core12C and core 12D are stacked. After the via is cut, copper is depositedforming the connection of two signal lines located in two core layers12D and 1B. Then core layer 12E is stacked with interconnect defined tooverlap and connect to the via.

FIGS. 10A and 10B show the schematic showing the enlarged top views ofthe signal line layout which is connecting to the via or microvia in thecase of multi-layered high speed PCB with the high speed signal linesand micro-via embedded into the PCB, in the seventh embodiment inaccordance to the invention, where in the like parts are indicated bythe like numerals, so that repeated explanation is omitted here.According to this invention, signal lines consisting of signal lines 58and 60 (located on the surface 62) may have/haven't have transition. Thetransition of the signal lines 58 with underneath air-cavities (openedtrenches) 24 (24A and 24B) to the signal lines 60 without air-cavities(opened trenches) prior to the via 54. For smooth transition withoutreflection of the signal, the transition length l₃ is used. The shape ofthe transition could be trapezoidal or circular or ellipsoidal (notshown).

FIGS. 11A, 11B, 11C, and 10D show the schematic showing the shape of theopening trenches into the core layers of the high speed PCB in theeighth embodiment in accordance to the invention, where in the likeparts are indicated by the like numerals, so that repeated explanationis omitted here. According to preferred embodiment, the opening can besquare shape 66, rectangular shape 68, trapezoidal shape 70, or circularshape 72 or ellipsoidal shape (not shown) where the top openings 74 canbe wider or similar to bottom opening 76. Noted here that the topopening 74 closer to the metal line (signal line or ground) than thebottom opening 76. The widths W₁, W₂, and W₃ of the top openings 74 canbe same or wider than the bottom openings 76. The widths W₁, W₂, and W₃as shown in FIGS. 11A, 11B, and 11C could be smaller, same or largerthan the signal lines width (not shown). In the case of the ellipsoidalor circular shaped openings 72, the width of the bottom openings can besmaller, same or larger than the signal lines width (not shown). Theheight (or deepness) of the openings can be adjusted based on thebandwidth requirements of the interconnects.

In the preferred embodiment as explained below, it is an object toprovide some calculated data for the high speed interconnects, explainedin FIGS. 12 to 14. These are the explanatory graphs showing theadvantages of the techniques. For each of the calculation as a PCBmaterial, epoxy-glass (trade name FR4) is used to show the performanceimprovement. As mentioned earlier, this invention covers also alldielectric materials having dielectric properties and can be used as theboard material. The present invention also covers all interconnects withopened trenches and utilize the semiconductor as the base material suchas silicon, GaAs, InP etc., to make high speed on-chip interconnects toconnect two or more electronic devices (e.g. transistors).

FIGS. 12A, 12B, and 12C show the estimated results for variation of thetangent loss and dielectric constant as the function of the dielectricremoval for the interconnects with opened trenches, in the ninthembodiment in accordance to the invention. Noted here that all theestimated results are for the conventional PCB materials for example FR4(epoxy-glass) or the dielectrics having the dielectric constant andtangent loss (dielectric loss) of 4.0 and 0.02, respectively. Thevariation of the dielectric constant and tangent loss from 4.0 and 0.02,respectively are due to the dielectric removal. The estimated dielectricconstant and dielectric loss are closer to the effective dielectricconstant and dielectric loss for the interconnects with dielectricremovals to open the trench. The effective dielectric constant andeffective dielectric loss for all dielectric removal (100%) are thoughtto be equivalent to 1.0 and 0.0, respectively. In the estimation, if notmentioned, the dielectrics removal width is considered as the same asthat of the signal line (metal) width. If the width of the trenches ismade wider than the signal line width, the less removal is necessary forthe achieved effective dielectric constant and effective tangent loss.

FIGS. 13A and 13B, and FIGS. 14A and 14B show the estimated results forvariation of the tangent loss and dielectric constant as the function ofthe dielectric removal for the interconnects having opened trenches, inthe tenth embodiment in accordance to the invention. The results asshown in FIGS. 13 and 14 are for the conventional PCB material forexample, FR4 and also for the assumption as already explained in FIGS.12, so that repeated explanation is omitted here. According to thisinvention, as the effective dielectric constant is reduced, it isnecessary to design/adjust the metal (signal line) width to keepcharacteristics impedance fixed. The signal line width is needed to keepwider than that of the signal line with no dielectric removal. FIGS. 13Aand 14A are the metal width variation as the function of the dielectricsremoval for the microstrip type and stripline type signal lines,respectively. 0.0% dielectric removal indicates the conventional typeinterconnects without opened trenches. 100% dielectric removal indicatesno-dielectrics under the signal lines, and in this case, effectivedielectric constant and effective dielectric loss are 1.0 and 0.0,respectively. FIGS. 13B and 14B are results showing the dielectricconstant versus signal line width with the dielectrics thickness are theparameters for the microstrip type and stripline type signal lines,respectively. These are shown for explanatory purpose to show thebenefits of this invention. All results shown here are for theinterconnects with 50 ohm characteristics impedance. As depicted, tokeep characteristics impedance fixed for example 50 ohm, either signalline width is needed to design wider or the thickness of dielectrics isneeded to be thinner than the interconnects without opened trenches.

FIG. 15 compares the frequency responses of the preferred embodiment inthe eleventh embodiment according to the invention. As explained inFIGS. 12 to 14, all results, according to this invention, are for theFR4 materials, as the conventional PCB material. Similar approach coversalso for other dielectric materials, which could be used as the PCBmaterial. According to this invention, the interconnects can be designedwith controlled bandwidth by removing the appropriate the dielectricsfrom the interconnects. As depicted, based on the percentage of thedielectric removal, the bandwidth can be increased to 20 GHz and above.

FIG. 16A is the top view and FIGS. 16B and 16C are cross-sectional viewsalong AA″ and BB″ directions of FIG. 16A in the twelfth preferredembodiment wherein the like parts are indicated by the like numerals, sothat similar explanations are omitted here. In the preferred embodiment,two chips interconnection on the PCB 77 are shown. As an example,processor 120 and memory 130 interconnection on PCB 77 are shown as anexample, and it comprises with high-speed signal lines 78, core layers80, prepreg to stack the several core layers 82, and the ground (powerline) 84. The core layers have the opened trenches 86, based on whetherthey carry the high-speed signal lines. The high speed signal line 78can be taken from the top of the PCB layer and lower speed signal linecan be take brought to the lower layer. This would reduce thepossibility any discontinuities, which may arise due to the vias.Bandwidth of the interconnects using of the technique as mentionedpreviously, can be attained and thereby on-chip's signal speed can bepreserved. For simplicity in drawing, enlarge portion of cross-sectionalviews for high speed (e.g. processor and memory) chips portioninterconnects are only shown. Complete PCB portion with consideringlower speed chip interconnects are not shown.

FIG. 17A is the top view and FIGS. 17B and 17C are enlargedcross-sectional views along AA″ and BB″ directions of FIG. 17A in thethirteenth preferred embodiment wherein the like parts are indicated bythe like numerals as used in FIGS. 4 and 16, so that similarexplanations are omitted here. In the preferred embodiment, two chipsinterconnection are shown. In the preferred embodiments, alternatively,the high-speed chips interconnect in the separate board 88, act as thefor multi-chip-module. For example for connecting the processor andmemory, board with back-trench or slot can be used and they can befabricated using the process along with the design as explained in FIGS.6 to 10. Each board has the pins 90 coming out from the outside of thePCB board 88 which can be mountable on to the motherboard made from theconventional PCB materials for more integration and for ground/power andlow speed connections.

The dielectric materials include all kinds of ceramic materials such asDuroid, PTFE, FR4, AlN, Al₂O₃, Mullite (3Al₂O₃:2SiO₂), SiC, SiO₂,Silicon nitride, Silicon-Oxy-Nitride, BeO, Cordie-rite (magnesiumalumina silicate), BN, Glass (with different compositions), epoxy glass,CaO, MnO, ZrO₂, PbO, alkali-halide (e.g. NaBr, NaCl) etc.) etc., and allkinds of the polyimides and benzocyclobutenes (BCBs) having dielectricproperties. Polymer dielectric material also includes, but not limitedto, Teflon, liquid crystal polymer, epoxy, parylene, silicone-polyimide,silicone-gel, and fluorinated ethylene propylene copolymer. It alsoincludes materials of elastomers (e.g. silicone elastomer), monomers,and gels. All standard polymers can be available from the standardmanufacturer for example, Du-pont, Nelco, General Electric, Isola,Hitachi-Chemical, Mitsui, and Mitsubishi-Chemical Industries. Gore-Tex,Japan, markets liquid crystal polymer.

According to this invention, semiconductor material such as Silicon,GaAs, InP, SiC, GaN, Ge etc. can also be used as the interconnect basematerial for making the high-speed on-chip interconnect to connect twoor more electron devices (e.g. transistors).

According to this invention, the opened trench can be filled with thecoolant so that by using this structure, the PCB cooling is alsopossible.

According to this invention, flow or no-flow type prepregs can be usedfor stacking the multiple core layers with signal or ground lines. It ishighly desirable to use thinner prepregs in order to get maximumperformances advantages. For prepreg materials, conventional availableprepregs, marketed by Polyclad corp, Arlon corp. etc. can be used. Theprepregs type could be flow or no-flow type based on the pressure andtemperature of the process during the stacking the core layers. In orderto avoid complete prevention of the prepreg from flowing into thetrenches, no flow type prepreg can be used. By process optimization thetrenches can be made to open as designed and the designed response canbe made to as close to the experimental response.

In the preferred embodiments, details process condition has not beendescribed. However, it would need to optimize the process condition toachieve the maximum performance. Absorption of the water during theprocess may occur. High temperature (below dielectric glass transitiontemperature) annealing before stacking removes the water molecules asabsorbed during or after the process. The water resistant-coating can beused on the trench surface after trench opened (and before stacking) toprevent the water or gas absorption during the process, which may reducethe reliability.

In the preferred embodiments as explained in FIGS. 12 to 15, only theFR4 based PCB design parameters are shown as an example. These resultshave been shown in an intention to show the benefits of this inventionand also to show the design ways for the interconnects according to thisinvention. Optimized design parameters may need based on the materialsparameters and interconnects structure and these can be achieved usingthe three-dimensional (3-D) field solution. For other dielectrics basedPCB (whether rigid or flex) similar design ways can be used forachieving the maximum performance.

In the preferred embodiments as explained in FIGS. 4 to 17, each coredielectric (sheet material) consisting of the dielectric and copper (orany metal) layer is considered for simplicity in explanation anddrawings. This invention also covers the PCB build-up made from the coreconsisting of the copper layer, dielectric and prepreg (epoxy). In thiscase, the process is the same as explained earlier. Only difference isto open the back-trench, which passes from epoxy (all portion) anddielectrics (percentage as necessary for bandwidth) (not shown here).For prepreg materials, conventional available prepregs, marketed byPolyclad corp, Arlon corp. etc. can be used. The prepregs type could beflow or no-flow type based on the pressure and temperature of theprocess during the stacking the core layers. In order to avoid completeprevention of the prepreg from flowing into the trenches, no flow typeprepreg can be used. By process optimization the trenches can be made toopen as designed and the designed response can be made to as close tothe experimental response.

In the preferred embodiments as explained in FIGS. 4 to 17, only stripline and microstrip line configurations are considered. However, inaccordance with the present invention, other signal lines, not mentionedhere, such as coplanar line configuration with single or multiple signallines (as single or differential) also include. Dielectric coverage (notshown) using of the same or different dielectric material can also beused.

In the preferred embodiments as explained in FIGS. 4 to 17, only square(or rectangular-shaped trenches are shown and they are opened at backside of the core-layer (i.e. opposite side of the signal lines). Thispresent inventions also cover trenches having any-shape convenient tothe manufacturing process and they could be located close proximity toand/or bottom (and top for strip lines) of the signal lines. The trenchcan be opened at the middle of the cross-section of the core layer.

In the preferred embodiments as explained in FIGS. 4 to 17, the groundplan is located close proximity to the prepreg and the opened trench (inthe case of the strip-type and microstrip type lines). This inventioncan also covered for the ground plan not located under (and over) thetrench openings. The ground plan can be located side of theopened-trenches.

The present invention has been described above by way of itsembodiments. However, those skilled in the art can reach various changesand modifications within the scope of the idea of the present invention.Therefore it is to be understood that those changes and modificationsalso belong to the range of this invention. For example, the presentinvention can be variously changed without departing from the gist ofthe invention, as indicated below.

The present invention has also been described above for the high speedrigid PCB. This technique to increase the bandwidth can also beimplemented into the high-speed flex-printed circuit fabrication.Related dielectric as appropriate can also be used for this purpose.

According to the present invention, it is the object to provide the highspeed PCB with interconnects having the opened trenches for reducing themicrowave loss for increasing the bandwidth of the interconnects. It isalso the object to use any dielectric material (including conventionaldielectric material and the manufacturing technology) in the techniqueand could increase the bandwidth tremendously. In simplicity of drawing,preferred embodiments are described mostly considering the microstripline and strip line configurations. However, all line configurationssuch as coplanar line with single or multiple signal line (includingdifferential line) also cover this invention.

According to the present invention, high speed PCB with interconnectsystem uses inhomogeneous dielectric system consisting of thedielectrics and the portion of air (or vacuum) layer to reduce theeffective dielectric loss and dielectric constant, wherein theinhomogeneous dielectric system has two or more dielectrics, and one ofthe dielectrics has lower dielectric loss. In the preferred embodiment,opened trench with air is used in the high speed PCB. Alternatively thelow dielectric loss (and/or dielectric constant) material or the liquidcrystal polymer fills up the trench.

According to this present invention, the dielectric and tangent lossvariation are estimated based on the assumption that the field isaccumulated under the signal lines, to show the advantages of thepreferred embodiments and to make it easy in estimation. In fact, theelectrical field is spread outside the signal line. More dielectricconstant and dielectric loss variation are possible if the trench widthis wider than the signal line-width, and they can be extended in bothside of the trench.

The present invention is described here, considering only onto thehigh-speed electrical signal. However, the present invention can be alsoused in the interconnects system where both electrical and opticalsignal can be transmitted using the same signal line. For example, thetrench portion is used to reduce the effective dielectric loss andeffective dielectric constant. By using the opened backside slot oropened trench the signal is mostly flowing through the trench filled upwith air or lower dielectric loss material. In the interconnects whereboth high speed electrical signal and high speed optical signal areconsidered, the trench or backside slot used can be used fortransmitting the optical and electrical signal together, and significantbandwidth of the interconnects system with high integration capabilitycan be realized.

Several preferred embodiments for high-speed off-chips interconnects andtheir manufacturing processes are described considering the microstripline (and also strip-line) configuration and also the dielectric systemwith back-trench or slot. All signal line configurations such asmicro-strip line, strip line or coplannaer type covers under thisinvention. The shape of the trench could be any type such as square,rectangular, circular, trapezoidal or any polynomial shape, or any shapeconvenient for manufacturing. These can be filled up by dielectricmaterial having the lower dielectric constant than the dielectricsubstrate.

According to this invention, the high speed interconnects on the PCB (orPWB) are disclosed. The fundamental techniques provided in thisinvention can also be used for high-speed packaging. More over, thisfundamental technology is also used for the high-speed die package canbe used and yet to increase the bandwidth of the interconnects.

Although the invention has been described with respect to specificembodiment for complete and clear disclosure, the appended claims arenot to be thus limited but are to be construed as embodying allmodification and alternative constructions that may be occurred to oneskilled in the art which fairly fall within the basic teaching here isset forth.

The present invention is expected to be found practically use in thehigh-speed on-chip, off-chip interconnects, where the signal speed 5Gb/s and beyond are necessary using of the conventional material, andthe bandwidth of the interconnects can be made to ideally to speed ofthe light for no-loss transmission line. The present invention can alsobe implemented in the high-speed single or multiple signal connectors,and high-speed cables (not shown). The applications include on-chipinterconnects where high-speed electronics chips or electronics chipswith optical chips are need to be connected. As ideally the bandwidth ofthe interconnect system can be made to close to fiber, future monolithic(and also hybrid near future) integration of electronics and opticalchips can also interconnected without (much or none at all) sacrificingthe chips speed. The application also includes the high speed multichipmodule interconnection, 3-D chip or memory interconnection, high speedparallel system for computer animation and graphics for high speed 2-Dor 3-D video transmission, and high bandwidth image display, high speedrouter where high speed electronics switches (or IC) are needed to beinterconnected. The application also include the high speed (5 Gb/s andbeyond) connectors and cables for high speed board-to-board,rack-to-rack interconnection, and also single or multiple high-densitysignal connections and carrying from one side to other in longer path.

1. A high speed printed circuit board (PCB) comprising; (a) a single orplurality of electrical signal lines, and; (b) a dielectric system,comprising; (i) a single or plurality layers of dielectrics with thesaid electrical signal lines and with open backside trench located underthe said electrical signal lines to reduce the microwave loss, and; (ii)a single or plurality layers of dielectrics with ground/power plan, anda single or multiple layers of the epoxies used as Prepreg to stackmultiple said dielectrics; wherein, the said electrical signal linelocated on the dielectrics are arranged as alternative layers with saidground/power plan in the said PCB.
 2. The process for building the saidhigh speed PCB as claimed in claim 1, with the microstrip-type signallines, comprises; (a) patterning and subsequent said electric signalline formation on the said dielectric; (b) opening the back-trench underthe signal line in the said dielectric, and; (c) stacking the saiddielectric having the signal lines and back-trench with anotherdielectric having the uniform metal plan in one side, with the saidprepreg; wherein, the prepreg is located in between two saiddielectrics.
 3. The process for building the said high speed PCB, withthe strip-type signal lines, comprises; (a) formation of the saidelectric signal line on the first dielectric; (b) opening theback-trench in the said first dielectric substrate; (c) opening the backtrench in the second dielectric substrate having the ground metal plan,and; (d) stacking the said first dielectric, second dielectric, and thethird dielectric with uniform metal plan by using of said prepreg inbetween two dielectrics.
 4. The process for building the said high speedPCB as claimed in claim 1, with the stripline type and microstrip typesignal lines, comprises; (a) signal line formation on the single orplurality of the dielectric substrate; (b) opening the back-trench inthe said single or plurality of dielectric substrate; (c) opening theback trench in the dielectric substrates having the ground metal plan,required on the top of the signal line for the case of stripline typesignal line, and; (d) stacking all dielectrics with signal lines oruniform metal plan by using of the prepreg in between two layers;wherein, the stripline has two trenches opening at top and bottomdielectrics, and microstrip line has one opening in back side of thedielectrics.
 5. The shape of the said opened backside trench as claimedin claim 1 is circular, cylindrical, spherical, trapezoidal, square etc.convenient to the manufacturing.
 6. The said electrical signal lines asclaimed in the claim 1 can be microstrip line type or strip line type orcoplanar type signal lines which are in single ended or differentialended.
 7. The PCB with the said microstrip line type signal lines asclaimed in claim 6 comprises; (a) single or plurality of electricalsignal lines; (b) dielectric substrate with opened trench under (andover) the signal lines; (c) a prepreg; (d) ground plan, and; (e)homogeneous dielectric substrate.
 8. The PCB with the said striplinetype signal lines the as claimed in claim 6 comprises; (a) a groundmetal plan; (b) dielectric substrate with opened trench aligned to theelectrical signal line(s); (c) a prepreg layer; (d) single of pluralityof said electrical signal lines; (e) a dielectric substrate with openedback trench aligned to the electrical signal line(s); (f) a prepreglayer; (g) ground plan, and; (h) homogeneous dielectric substrate. 9.The said single or plurality of signal lines as claimed in claim 1 hasthe coplanar line configuration, wherein the signal line(s) and groundplan are in the same plan and laid on the said dielectric system asclaimed in claim 1, and also are exposed to either the dielectric mediaor in air media.
 10. The said slot or trench as claimed in claim 1 isfilled with the air or lower dielectric loss as compared with the basedielectric.
 11. The said slot or trench as claimed in claim 1 is filledup or coated by the liquid crystal polymer to have the tunability of thedielectric loss (or dielectric constant).
 12. The backside trench asclaimed in claim 1 can be opened by the laser drilling, mechanicaldrilling, wet-etching, or dry-etching techniques.
 13. Laser drilling asclaimed in claim 12 can be performed by using the CO₂ laser, UV laser,Excimer laser or Nd:Yag laser.
 14. The dry-etching as claim in claim 12can be performed by plasma etching using the mixture of C—F type gaseswith Oxygen.
 15. The wet etching as claimed in claim 12 can be performedusing the mixture of NaOH, KMnO₂, and buffered HF.
 16. The signal linespassing from one layer to other layers through via or microvia of thesaid high speed PCB, has two or more sections on the same dielectrics,comprising; (a) first section of signal lines with the opened trench inthe dielectric(s), and; (b) second section of signal lines withoutopened trench in the dielectrics connects the said first section of thesignal lines and the via or microvia; wherein, the signal line withopened trench has the wider width than that of the signal lines withoutopened trench.
 17. The said prepreg as claimed in claim 1 is eitherno-flow or flow prepreg for stacking multiple dielectrics.
 18. The saidprepreg as claimed in claim 1 can be Arlon 47N, Arlon 49N and Isola406NF.
 19. The materials of the said dielectrics system as claimed inclaim 1 cover all kinds of materials showing dielectric properties. 20.The said materials as claimed in claim 19 cover epoxy-glass (FR4),Kepton, polymer, resin, alumina, boron nitride, silicon oxide, aluminumnitride, low temperature or high temperature ceramics, silicon nitride,PTFE, duroid, rogers, nelcos materials, or Q-PILON etc.
 21. The saidhigh speed PCB as claimed in claim 1 cover rigid circuit board, flexcircuit board, or combination of both.
 22. The said prepreg as claimedin claim 1 is continuous layer and located in-between two dielectrics tostack them.
 23. The said prepreg as claimed in claim 1 can bediscontinuous, wherein no prepreg layer is exist in the opening portionof the said trench as claimed in claim
 1. 24. The trench as claimed inclaim 1 can be also filled with coolant to cool the said PCB.
 25. Theopen trench as claimed in claim 1 is located at bottom of the signalline for the microstrip type signal line or located both on top andbottom of the signal lines for the stripline type signal lines.